The present invention relates to semiconductor devices and methods of forming the same. More specifically, the present invention is directed to a one transistor DRAM device and a method of forming the same.
The semiconductor device includes a non-volatile memory such as a DRAM. Typically, a unit cell of a DRAM includes one transistor and one capacitor. The difficulty level of a process of forming capacitors having the same capacitance is increasing with the recent trend toward higher integration density of semiconductor devices.
A variety of attempts have been made to overcome the increasing difficulty level of the process. One of these attempts is to develop a one transistor DRAM cell structure where there is one transistor and no capacitor. That is, the one transistor DRAM cell is advantageous in achieving a high integration density because there is no capacitor.
Referring to FIG. 1, a conventional one transistor DRAM cell is formed on a semiconductor substrate 10 including a filling insulating layer 11. A source region 14, a floating body 13, and a drain region 15 are provided on the filling insulating layer 11. A gate insulator 16 and a gate pattern 18 are sequentially provided on the floating body 13. The source region 14, the drain region 15, and the gate pattern 18 are connected to a ground, a bitline, and a wordline, respectively. The floating body 15 is electrically isolated by the filling insulating layer 11, the gate insulator 16, the source region 14, and the drain region 15. The one transistor DRAM cell can store and read data using the floating body effect.
A write operation of the one transistor DRAM cell, i.e., a data storing method is now described. The source region 14 is grounded. A wordline voltage higher than a threshold voltage is applied to the gate pattern 18. A bitline program voltage is applied to the drain region 15. The write operation includes generating holes at the floating body 13 in the vicinity of the drain region 15. The holes are accumulated in the floating body 13. The accumulated holes result in fluctuation of the threshold voltage.
A read operation of the one transistor DRAM cell, i.e., a data reading method is now described. The source region 14 is grounded. A wordline read voltage lower than the wordline program voltage is applied to the gate pattern 18. A bitline read voltage is applied to the drain region 15. The amount of current flowing between the source region 14 and the drain region 15 varies depending on whether there are holes. That is, the amount of current flowing between the source region 14 and the drain region 15 is detected to read data stored in the one transistor DRAM cell. In addition, the threshold voltage varies with the amount of the accumulated holes.